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HIGH SPEED 64K (4K X 16 BIT) IDT70824S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAMTM)
Features
x x x x
x
x
x
x
High-speed access - Military: 35/45ns (max.) - Commercial: 20/25/35/45ns (max.) Low-power operation - IDT70824S Active: 775mW (typ.) Standby: 5mW (typ.) - IDT70824L Active: 775mW (typ.) Standby: 1mW (typ.) 4K x 16 Sequential Access Random Access Memory (SARAMTM) - Sequential Access from one port and standard Random Access from the other port - Separate upper-byte and lower-byte control of the Random Access Port High speed operation - 20ns tAA for random access port - 20ns tCD for sequential port - 25ns clock cycle time Architecture based on Dual-Port RAM cells
x x x x x
Compatible with Intel BMIC and 82430 PCI Set Width and Depth Expandable Sequential side - Address based flags for buffer control - Pointer logic supports up to two internal buffers Battery backup operation - 2V data retention TTL-compatible, single 5V (+10%) power supply Available in 80-pin TQFP and 84-pin PGA Military product compliant to MIL-PRF-38535 QML Industrial temperature range (-40C to +85C) is available for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random Access Memory (SARAM). The SARAM offers a single-chip solution to buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM based architecture with a standard SRAM interface for the random (asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
A0-11 CE OE R/W LB LSB MSB UB CMD I/O0-15
12
Random Access Port Controls
Sequential Access Port Controls
4K X 16 Memory Array
16 12 12 12 12 12
RST SCLK CNTEN SOE SSTRT1 SSTRT2 SCE SR/W SLD SI/O0-15 ,
DataL AddrL
DataR AddrR
16
Reg. 12
16
RST
Pointer/ Counter
Start Address for Buffer #1 End Address for Buffer #1 Start Address for Buffer #2 End Address for Buffer #2 Flow Control Buffer Flag Status
12
EOB1 COMPARATOR EOB2
3099 drw 01
APRIL 2000
1
(c)2000 Integrated Device Technology, Inc. DSC-3099/5
6.07
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
quencing for the sequential (synchronous) access port. Fabricated using CMOS high-performance technology, this memory device typically operates on less than 775mW of power at maximum highspeed clock-to-data and Random Access. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
The IDT70824 is packaged in a 80-pin Thin Quad Flatpack (TQFP) or 84-pin Pin Grid Array (PGA). Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
INDEX SI/O1 SI/O0 GND N/C SCE SR/W RST SLD SSTRT2 SSTRT1 GND GND CNTEN SOE SCLK GND EOB2 EOB1 VCC I/O0
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 2 58 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 57 56 55 54 53
SI/O2 SI/O3 VCC SI/O4 SI/O5 SI/O6 SI/O7 GND SI/O8 SI/O9 SI/O10 SI/O11 VCC SI/O12 SI/O13 SI/O14 SI/O15 GND N/C GND
IDT70824PF PN80-1(4) 80-Pin TQFP Top View(5)
52 51 50 49 48 47 46 45 44 43 42 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Configurations(1,2,3)
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC VCC A1 A0 CMD CE LB UB R/W OE
3099 drw 02 ,
63
61
I/O1 GND I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 VCC I/O12 I/O13 I/O14 I/O15 GND
60 58 55 54 51 SSTRT2 50 48 46 45 42
I/O1
66
VCC
64
EOB1
62
GND CNTEN GND
59 56 49
SR/W NC
47 44
GND
43
NC
40
11 10 09 08 07 06 05 04 03 02 01
,
I/O2
67
NC
65
I/O0 EOB2 SOE RST SLD
57 53 52 SSTRT1
SCE SI/O0 SI/O1 SI/O3
41 39
I/O3 GND
69 68
SCLK GND
SI/O2 VCC
38 37
I/O4
72
VCC
71 73 33
SI/O4 SI/O5
35 34
I/O7
75
I/O6 GND
70 74
IDT70824G G84-3(4) 84-Pin PGA Top View(5)
SI/O8 SI/O7 GND
32 31 36
I/O9
76
I/O5
77
I/O8
78
SI/O9 SI/O10 SI/O6
28 29 30
I/O10 I/O11 VCC
79 80
SI/O12 VCC SI/O11
26 27
I/O12 I/O13
81 83 7 11 12
SI/O14 SI/O13
23 25
I/O14
82 1
NC
2 5
CMD VCC
8 10
A2
14 17 20
NC SI/O15
22 24
I/O15 GND
84 3 4
OE
6
LB
9
A0 A1 E
VCC
15
A4
13
A7
16
A10
18
GND GND
19 21
NC A Pin 1 Designator
R/W B
UB C
CE D
A5 F
A3 G
A6 H
A8 J
A9 K
A11 L
3099 drw 03
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
2
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Pin Descriptions: Random Access Port(1)
SYMBOL A0-A11 I/O0-I/O15 CE NAME Address Lines Inputs/Outputs Chip Enable I/O I I I DESCRIPTION Address inputs to access the 4096-word (16-Bit) memory array. Random access data inputs/outputs for 16-Bit wide data. When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port CE and CMD may not be LOW at the same time. When CMD is LOW, address lines A0-A2, R/W, and inputs and outputs I/O0-I/O12, are used to access the control register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the same time. If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in the High-impedance state. When LB is LOW, I/O0-I/O7 are accessible for re ad and write operations. When LB is HIGH, I/O0-I/O7 are tristated and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and is asynchronous from LB. Seven +5 power supply pins. All VCC pins must be connected to the same +5V VCC supply. Ten ground pins. All ground pins must be connected to the same ground supply.
3099 tbl 01
CMD
Control Register Enable
I
R/W
Read/Write Enable
I
OE LB, UB
Output Enable Lower Byte, Upper Byte Enables
I I
VCC GND
Power Supply Ground
I I
Pin Descriptions: Sequential Access Port(1)
SYMBOL SI/O0-15 SCLK SCE NAME Inputs/Outputs Clock Chip Enable I/O I/O I I DESCRIPTION Sequential data inputs/outputs for 16-bit wide data. SI/O0-SI/O15,SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential access port address pointer increments by 1 on each LOW-TO-HIGH transition of SCLK when CNTEN is LOW. When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transitio n of SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the High-impedance state. All data is retained , unless altered by the random access port. When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is independent of CE. When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination o f a write cycle is done on the LOW-to -HIGH transition of SCLK if SR/W or SCE is HIGH. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the datain register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. EOB1 or EOB2 is output low when the address pointer is incremented to match the address stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or by writing ze ro into Bit 0 and/or Bit 1 of the control registe r at address 101. EOB1 and EOB2 are dependent on separate internal registers, and therefore separate match addresses. SOE controls the data outputs and is independe nt of SCLK. When SOE is LOW, output buffers and the se quentially ad dressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state. SOE is asynchronous to SCLK. When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
3099 tbl 02
CNTEN SR/W
Counter Enable Read/Write Enable
I I
SLD
Address Pointer Load Control
I
SSTRT1, SSTRT2 EOB1, EOB2
Load Start of Address Register End of Buffer Flag
I
O
SOE
Output Enable
I
RST
Reset
I
NOTE: 1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.42 3
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Absolute Maximum Ratings
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0
(1)
Unit V
Military -0.5 to +7.0
Recommended Operating Temperature and Supply Voltage
Grade Ambient Temperature Military -55OC to +125OC 0OC to +70OC -40 C to +85 C
O O
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
3099 tbl 04
TBIAS TSTG IOUT
-55 to +125 -55 to +125 50
-65 to +135 -65 to +150 50
o
C C
Commercial Industrial
o
mA
3099 tbl 03
NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating Conditions
Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0
____
Max. 5.5 0 6.0
(2)
Unit V V V V
3099 tbl 05
Capacitance
Symbol CIN COUT
VIH VIL
(TA = +25C, f = 1.0mhz, TQFP only)
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
3099 tbl 06
____
0.8
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. This parameter is determined by device characterization, but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
70824S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCC VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
___ ___ ___
70824L Max. 5 5 0.4
___
Min.
___ ___ ___
Max. 1 1 0.4
___
Unit A A V V
3099 tbl 07
2.4
2.4
4
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2,8) (VCC = 5.0V 10%)
70824X20 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CEL and CER = VIL, Outputs Open SCE = VIL(5) f = fMAX(3) SCE and CE = VIH(7) CMD = VIH f = fMAX(3) Version COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ.(2) 180 180
____ ____
70824X25 Com'l Only Typ.(2) 170 170
____ ____
70824X35 Com'l & Military Typ.(2) 160 160 160 160 20 20 20 20 95 95 95 95 1.0 0.2 1.0 0.2 90 90 90 90 Max. 340 290 400 340 70 50 85 65 240 210 290 250 15 5 30 10 220 180 260 215
70824X45 Com'l & Military Typ.(2) 155 155 155 155 16 16 16 16 90 90 90 90 1.0 0.2 1.0 0.2 85 85 85 85 Max. 340 290 400 340 70 50 85 65 240 210 290 250 15 5 30 10 220 180 260 215
3099 tbl 08
Max. 380 330
____ ____
Max. 360 310
____ ____
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
25 25
____ ____
70 50
____ ____
25 25
____ ____
70 50
____ ____
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
CE or SCE = VIH Active Port Outputs Open, f=fMAX(3)
115 115
____ ____
260 230
____ ____
105 105
____ ____
250 220
____ ____
mA
ISB3
Full Standby Current (Both Ports CMOS Level Inputs)
Both Ports CE and SCE > VCC - 0.2V(6) VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) One Port CE or SCE > VCC - 0.2V(6,7) Outputs Open (Active Port) f = fMAX(3) VIN > VCC - 0.2V or VIN < 0.2V
1.0 0.2
____ ____
15 5
____ ____
1.0 0.2
____ ____
15 5
____ ____
mA
ISB4
Full Standby Current (One Port CMOS Level Inputs)
110 110
____ ____
240 200
____ ____
100 100
____ ____
230 190
____ ____
mA
NOTES 1. 'X' in part number indicates power rating (S or L). 2. VCC = 5V, TA = +25C; guaranteed by device characterization but not production tested. 3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC. 4. f = 0 means no address or control lines change. 5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK. 6. SCE may be - 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown. 7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and TTL HIGH = VIH and LOW = VIL. 8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current VCC = 2V CE = VHC VIN = VHC or = VLC tCDR (3) tR(3) Chip Deselect to Data Retention Time Operation Recovery Time MIL. & IND. COM'L. Test Condition Min. 2.0
___
Typ. (1)
___
Max.
___
Unit V A
100 100
___
4000 1500
___
___
SCE = VHC(4) when SCLK = u CMD > VHC
___
V V
3099 tbl 09
tRC(2)
___
___
NOTES : 1. TA = +25C, VCC = 2V; guaranteed by device characterization but not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization, but is not production tested. 4. To initiate data retention, SCE = VIH must be clocked in.
6.42 5
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Data Retention Power Down/Up Waveform (Random and Sequential Port)(1,2)
DATA RETENTION MODE VCC 4.5V tCDR CE VIH VDR VDR 2V 4.5V tR VIH
SCLK
SCE tPD ICC ISB
NOTES : 1. SCE is synchronized to the sequential clock input. 2. CMD > VCC - 0.2V.
tPU
ISB
3099 drw 04
5V 893 DATAOUT 347 30pF DATAOUT 347
5V 893
5pF*
3099 drw 05
3099 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ, tBHZ, tOHZ,tWHZ, tCKHZ, and tCKLZ) (*Including scope and jig.)
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3
3099 tbl 10
8 7 6 tAA/tCD/tEB 5 (Typical, ns) 4 3 2 1 -1 -2 -3 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF)
3099 drw 07 ,
10pF is the I/O capacitance of this device, and 30pF is the AC Test Load capacitance.
Figure 3. Lumped Capacitance Load Typical Derating Curve
6
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table I: Random Access Read and Write(1,2)
Inputs/Outputs CE L L L L L L H L L H H CMD H H H H H H H H H L L R/W H H H L L L X H X L H OE L L L H H
(3) (3) (3)
LB L L H L L H X X H L
(4) (4)
UB L H L L H L X X H L L
(4) (4)
I/O0-I/O7 DATAOUT DATAOUT High-Z DATAIN DATAIN High-Z High-Z High-Z High-Z DATAIN DATAOUT
I/O8-I/O15 DATAOUT High-Z DATAOUT DATAIN High-Z DATAIN High-Z High-Z High-Z DATAIN DATAOUT Read both Bytes. Read lower Byte only. Read upper Byte only. Write to both Bytes. Write to lower Byte only. Write to upper Byte only.
MODE
H X
Both Bytes deselected and powered down. Outputs disabled but not powered down. Both Bytes deselected but not powered down. Write I/O0-I/O11 to the Buffer Command Register. Read contents of the Buffer Command Register via I/O0-I/O12.
H X H L
(3)
L
3099 tbl 11 NOTES: 1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. 2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation. 3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven. 4. Byte operations to control register using UB and LB separately are also allowed.
Truth Table II: Sequential Read(1,2,3,6,8)
Inputs/Outputs SCLK SCE L L L L L CNTEN L H L H L SR/W H H H H H EOB1 LOW LAST LAST LAST LOW EOB2 LAST LAST LOW LAST LOW SOE L L L L H SI/O [EOB1] [EOB1 - 1] [EOB2] [EOB2 - 1] High-Z MODE Counter Advanced Sequential Read with EOB1 reached. Non-Counter Advanced Sequential Read, without EOB1 reached Counter Advanced Sequential Read with EOB2 reched. Non-Counter Advanced Sequential Read without EOB2 reached Counter Advanced Sequential Non-Read with EOB1 and EOB2 reached
3099 tbl 12
Truth Table III: Sequential Write(1,2,3,4,5,6,7,8)
Inputs/Outputs SCLK SCE L L H H CNTEN H L H L SR/W L L X X EOB1 LAST LOW LAST NEXT EOB2 LAST LOW LAST NEXT SOE H H X X SI/O SI/OIN SI/OIN MODE Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached. Counter Advanced Sequential Write with EOB1 and EOB2 reached.
High-Z No Write or Read due to Sequential port Deselect. No counter advance. High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
3099 tbl 13 NOTES: 1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL. 2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations. 3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock during the cycle in which SR/W = VIL. 5. SI/OIN refers to SI/O0-SI/O15 inputs. 6. "LAST" refers to the previous value still being output, no change. 7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH. 8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after Reset, Read (and write) Cycle".
6.42 7
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table: Sequential Address Pointer Operations(1,2,3,4,5)
Inputs/Outputs SCLK SLD H H L SSTRT1 L H H SSTRT1 H L H SOE X X MODE Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached. Counter Advanced Sequential Write with EOB1 and EOB2 reached.
H(6) No Write or Read due to Sequential port Deselect. No counter advance.
3099 tbl 14
NOTES: 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. 2. RST is continuously HIGH. The conditions of SCE CNTEN, and SR/W are unrelated to the sequential address pointer operations. 3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table. 5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented during the two cycles. 6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
In SLD mode, there is an internal delay of one cycle before the address pointer changes in the cycle following SLD. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-toHIGH transition of SCLK. On the cycle following SLD, the address pointer
Address Pointer Load Control (SLD)
changes to the address location contained in the data-in register. SSTRT1, SSTRT2 may not be low while SLD is LOW, or during the cycle following SLD. The SSTRT1 and SSTRT2 require only one clock cycle, since these addresses are pre-loaded in the registers already.
SLD Mode(1)
SLD
(1)
SCLK
A SI/O0-11 ADDRIN
B
C DATAOUT
SSTRT(1 or 2)
3099 drw 08
NOTE: 1. At SCLK edge (A), SI/O0-SI/O11 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e. address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B), SLD and SSTRT1,2 must be HIGH to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
Sequential Load of Address into Pointer/Counter(1)
15 MSB H 14 H 13 H 12 L 11 -------------------------------------------------------------------------------------------------- 0 Address Loaded into Pointer LSB SI/O BITS
3099 drw 09
NOTE: 1. "H" = VIH and "L" = VIL for the SI/O intput state.
8
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Reset (RST)
Setting RST LOW resets the control state of the SARAM. RST functions asynchronously of SCLK (i.e. not registered). The default states after a reset operation are displayed in the adjacent chart.
Address EOB Flags
Register
Contents 0 Cleared to HIGH state BUFFER CHAINING 0 (1) 4095 (4K)
(1)
Buffer Flow Mode Start Address Buffer #1 End Address Buffer #1 Start Address Buffer #2 End Address Buffer #2 Registered State
Cleared (set at invalid points) Cleared (set at invalid points) SCE = VIH, SR/W = VIL
3099 tbl 15
(1)
NOTE: 1. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode" section.
Buffer Command Mode (CMD)
Buffer Command Mode (CMD) allows the random access port to control the state of the two buffers. Address pins A0-A2 and I/O pins I/O0I/O11 are used to access the start of buffer and the end of buffer addresses and to set the flow control mode of each buffer. The Buffer Command Mode also allows reading and clearing the status of the EOB flags. Seven different CMD cases are available depending on the conditions of A0-A2 and R/ W. Address bits A3-A11 and data I/O bits I/O12-I/O15 are not used during this operation.
Random Access Port CMD Mode(1)
Case # 1 2 3 4 5 6 7 8 A2-A0 000 001 010 011 100 101 101 110/111 R/W 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 1 (X) DESCRIPTIONS Write (read) the start address of Buffer #1 through I/O0-I/O11. Write (read) the end address of Buffer #1 through I/O0-I/O11. Write (read) the start address of Buffer #2 through I/O0-I/O11. Write (read) the end address of Buffer #2 through I/O0-I/O11. Write (read) flow control register. Write only - clear EOB1 and/or EOB2 flag. Read only - flag status register. (Reserved)
3099 tbl 16
NOTE: 1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Cases 1 through 4: Start and End of Buffer Register Description(1,2)
15 MSB H 14 H 13 H 12 L 11 -------------------------------------------------------------------------------------------------- 0 Address Loaded into Buffer LSB I/O BITS
3099 drw 10
NOTES: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = VIL for I/O in the input state. 2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and CE = VIH.
Case 5: Buffer Flow Modes
Within the SARAM, the user can designate one of two buffer flow modes for each buffer. Each buffer flow mode defines a unique set of actions for the sequential port address pointer and EOB flags. In BUFFER CHAINING mode, after the address pointer reaches the end of the buffer, it sets the corresponding EOB flag and continues from the start address of the other buffer. In STOP mode, the address pointer stops incrementing after it reaches the end of the buffer. There is no linear or mask mode available.
6.42 9
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Flow Control Register Description
15 MSB H H H H H H H H
(1,2)
0 H H H 4 3 2 1 0 LSB I/O BITS
Counter Release (STOP Mode Only)
Buffer #1 flow control
Buffer #2 flow control 3099 drw 11 NOTES: 1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state. 2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT2 operations.
Flow Control Bits(5)
Flow Control Bit 1 & Bit 0 (Bit 3 & Bit 2) 00 01 Mode BUFFER CHAINING STOP Functional Description EOB1 (EOB2) is asserted (Active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1)(1,3) EOB1 (EOB2) is asserted when the pointer matches the end address of Butler #1 (Butler #2). The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is LOW on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register. (1,2,4)
3099 tbl 17
NOTES: 1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value. 2. CMD flow control bits are unchanged, the count does not continue advancement. 3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1. 4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise the flow control will remain in the stop mode. 5. Flow Control Bit settings of '10' and '11' are reserved. 6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode" section. RST conditions are not set to valid addresses.
Cases 6 and 7: Flag Status Register Bit Description(1)
15 MSB H H H H H H H H H H H H H H 1 0 0 LSB I/O BITS
NOTE: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
End of buffer flag for Buffer #1 End of buffer flag for Buffer #2
3099 drw 12
Cases 6: Flag Status Register Write Conditions(1)
Flag Status Bit 0, (Bit 1) 0 1 Functional Description Clears Buffer Flag EOB1, (EOB2). No chang e to the Buffer Flag. (2)
3099 tbl 18
Case 7: Flag Status Register Read Conditions
Flag Status Bit 0, (Bit 1) 0 Functional Description EOB1 (EOB2) flag has not been set, the Pointer has not reached the End of the Buffer. EOB1 (EOB2) flag has been set, the Pointer has reached the end of the Buffer.
3099 tbl 19
NOTES: 1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone, or both may be cleared. 2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
1
Cases 8 and 9: (Reserved)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
10
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(2,4,5)
70824X20 Com'l Only Symbol READ CYCLE tRC tAA tACE tBE tOE tOH tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Select Low-Z Time Byte Select Low-Z Time
(1) (1) (1)
70824X25 Com'l Only Min. Max.
70824X35 Com'l & Military Min. Max.
70824X45 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20
____
____
25
____
____
35
____
____
45
____
____
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3099 tbl 20
20 20 20 10
____
25 25 25 10
____
35 35 35 15
____
45 45 45 20
____
____
____
____
____
____
____
____
____
____
____
____
____
3 3 3 2
____
3 3 3 2
. ____
3 3 3 2
____
3 3 3 2
____
____
____
____
____
____
____
____
____
Output Enable Low-Z Time Chip Select High-Z Time (1) Byte Select High-Z Time
(1)
____
____
____
____
10 10 9
____
12 12 11
____
15 15 15
____
15 15 15
____
____
____
____
____
Output Select High-Z Time
(1)
____
____
____
____
Chip Select Power-Up Time Chip Select Power-Down Time
0
____
0
____
0
____
0
____
20
25
35
45
Random Access Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(2,4,5)
70824X20 Com'l Only Symbol WRITE CYCLE tWC tCW tAW tAS tWP tBP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width
(3) (3) (3)
70824X25 Com'l Only Min. Max.
70824X35 Com'l & Military Min. Max.
70824X45 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20 15 15 0 13 15 0
____
____
25 20 20 0 20 20 0
____
____
35 25 25 0 25 25 0
____
____
45 30 30 0 30 30 0
____
____
ns ns ns ns ns ns ns ns ns ns ns
3099 tbl 21
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Byte Enable Pulse Width Write Recovery Time
____
____
____
____
____
____
____
____
Write Enable Output High-Z Time (1) Data Set-up Time Data Hold Time Output Active from End-of-Write
10
____
12
____
15
____
15
____
13 0 3
15 0 3
20 0 3
25 0 3
____
____
____
____
____
____
____
____
NOTES: 1. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production tested. 2. 'X' in part number indicates power rating (S or L). 3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing. 4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = VIL). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42 11
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Read Cycles: Random Access Port(1,2)
tRC ADDR tAA CE tCLZ LB, UB tBE tBLZ OE tOE tOLZ I/OOUT Valid Data Out
3099 drw 13
tOH tACS
(2)
tCHZ
tBHZ
tOHZ
NOTES: 1. R/W is HIGH for read cycle. 2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
Waveform of Read Cycles: Buffer Command Mode
tRC ADDR tAA CMD
(1)
tOH tACS
tCLZ LB, UB tBE tBLZ OE tOE tOLZ I/OOUT Valid Data Out
tCHZ
tBHZ
tOHZ
3099 drw 14
NOTE: 1. CE = VIH when CMD = VIL.
12
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycle No.1 (R/W Controlled Timing) Random Access Port(1,6)
tWC ADDR tAW R/W tAS CE, LB, UB
(8) (5)
tWP(2)
tWR(3)
tDW I/OIN OE tWHZ I/OOUT Data Out
(4)
tDH
Valid Data In
tOHZ
(4)
Data Out
tACS tBE
tOW
3099 drw 15
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing) Random Access Port(1,6,7)
tWC ADDR tAW CE, LB, UB
(8) (5)
tAS R/W
tCW tBP(2)
(2)
tWR
(3)
tDW I/OIN Valid Data
tDH
3099 drw 16
NOTES: 1. R/W, CE, or LB and UB must be inactive during all address transitions. 2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL. 3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state and the input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing. 7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle. 8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
6.42 13
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,3)
70824X20 Com'l Only Symbol READ CYCLE tCYC tCH tCL tES tEH tSOE tOLZ tOHZ tCD tCKHZ tCKLZ tEB Sequential Clock Cycle Time Clock Pulse HIGH Clock Pulse LOW Count Enable and Address Pointer Set-up Time Count Enable and Address Pointer Hold Time Output Enable to Data Valid Output Enable Low-Z Time(2) Output Enable High-Z Time Clock to Valid Data Clock High-Z Time(2) Clock Low-Z Time Clock to EOB
(2) (2)
70824X25 Com'l Only Min. Max.
70824X35 Com'l & Military Min. Max.
70824X45 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
25 10 10 5 2
____
____
30 12 12 5 2
____
____
40 15 15 6 2
____
____
50 18 18 6 2
____
____
ns ns ns ns ns ns ns ns ns ns ns ns
3099 tbl 22
____ ____ ____ ____
____ ____ ____ ____
____ ____ ____ ____
____ ____ ____ ____
8
____
10
____
15
____
20
____
2
____ ____ ____
2
____ ____ ____
2
____ ____ ____
2
____ ____ ____
9 20 12
____
11 25 14
____
15 35 17
____
15 45 20
____
3
____
3
____
3
____
3
____
13
15
18
23
Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(1,3)
70824X20 Com'l Only Symbol WRITE CYCLE tCYC tFS tWS tWH tDS tDH Sequential Clock Cycle Time Flow Restart Time Chip Select and Read/Write Set-up Time Chip Select and Read/Write Hold Time Input Data Set-up Time Input Data Hold Time 25 13 5 2 5 2
____
70824X25 Com'l Only Min. Max.
70824X35 Com'l & Military Min. Max.
70824X45 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
30 15 5 2 5 2
____
40 20 6 2 6 2
____
50 20 6 2 6 2
____
ns ns ns ns ns ns
3099 tbl 23
____ ____ ____ ____
____ ____ ____ ____
____ ____ ____ ____
____ ____ ____ ____
____
____
____
____
NOTES: 1. 'X' in part number indicates power rating (S or L). 2. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production tested. 3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
14
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(1,2)
70824X20 Com'l Only Symbol WRITE CYCLE tRSPW tWERS tRSRC tRSFV Reset Pulse Width Write Enable HIGH to Reset HIGH Reset HIGH to Write Enable LOW Reset HIGH to Flag Valid 13 10 10 15
____ ____ ____
70824X25 Com'l Only Min. Max.
70824X35 Com'l & Military Min. Max.
70824X45 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
15 10 10 20
____ ____ ____
20 10 10 25
____ ____ ____
20 10 10 25
____ ____ ____
ns ns ns ns
3099 tbl 24
____
____
____
____
NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Sequential Port: Write, Pointer Load Non-Incrementing Read
tCYC tCH SCLK tES CNTEN tES SLD tDS SI/OIN Dx tWS tWH SR/W tWS tWH SCE tCD SOE tSOE tOLZ SI/OOUT tCKLZ
NOTES: 1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
tCL tEH
(3) (2)
tEH
(1)
tDH HIGH IMPEDANCE tWS tWH tWS
A0
tWH tCSZ tCKHZ tOHZ D0 D0 D0
3099 drw 17
6.42 15
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: Write, Pointer Load, Burst Read
tCH SCLK CNTEN tES SLD tDS SI/OIN Dx tWS SR/W tWS SCE tSD SOE SI/OOUT tSOP tOLZ D0 D1 tCKLZ NOTES: 1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW. tOHZ
(2) 3099 drw 18
tCYC tCL tES
(3)
tEH
(2)
tEH
(1)
tDH HIGH IMPEDANCE tWS tWS tWH
tDS
tDH
A0 tWH tWH
D2
tWH
Read STRT/EOB Flag Timing - Sequential Port
tCH SCLK CNTEN tES SSTRT1/2 tEH
(1)
tCYC tCL tES
(4)
tEH
(2)
tDS SI/OIN Dx tWS SR/W tWS SCE SOE SI/OOUT EOB1/2 tWH
(3)
HIGH IMPEDANCE tWS tWH tWS tWH
tDH
D3
tWH
tCD tSOE tOLZ
(5)
tOHZ D0 tCKLZ tEB
3099 drw19
D1
D2
(2)
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing") 1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write on this cycle. 4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT. 5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH. 6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
16
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port
tCH SCLK tES CNTEN tES SLD tDS SI/OIN Dx tWS SR/W tWS SCE tCD SOE SI/OOUT tCKLZ
(5) (3)
tCYC tCL tEH tES tEH
(4)
tEH
(1)
tDH
tDS D0 tWS tWH
tDS tDH HIGH IMPEDANCE D1
tDH
A0 tWH
(4)
tWH
tWS
tWH tCKHZ
D0
tOHZ HIGH IMPEDANCE
3099 drw 20
Waveform of Burst Write Cycles: Sequential Port
tCH SCLK CNTEN tES SLD tDS SI/OIN Dx tWS SR/W tWS SCE SOE HIGH IMPEDANCE tWH tWS tWH tWH A0 tEH
(1)
tCYC tCL tES
(3)
tEH
(2)
tDS tDH D0 tWS tWH
(5)
tDH D1 D2
(5)
tCKLZ tCD
SI/OOUT
D2
3099 drw 21
NOTES: 1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is LOW. 4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH. 5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.42 17
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
tCH SCLK tCL tEH
(2)
tES CNTEN tES SSTRT1/2 tEH
(1) (4)
tDS tDH SI/OIN Dx tWS SR/W tWS SCE tWS tWH
(3)
D0 tWH
D1 tWS tWH
D2
D3
HIGH IMPEDANCE
(5)
tWH
SOE HIGH IMPEDANCE
(6)
tCKLZ tCD
SI/OOUT EOB1/2
D3 tEB
3099 drw 22
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing") 1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge. 2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance. 3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write on this cycle. 4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT. 5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH. 6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
18
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Counter Enable Cycle After Reset, Write Cycle(1,4,6)
SCLK
RST
CNTEN
(2)
SI/OIN
D0
D1
D2
D3
D4
3099 drw 23
Sequential Counter Enable Cycle After Reset, Read Cycle(1,4)
SCLK
RST SR/W
(3)
CNTEN
(5)
SI/OOUT
D0
(5)
D1
D2
D3
3099 drw 24
NOTES: 1. 'D0' represents data input for Address = 0, 'D1' represents data input for Address = 1, etc. 2. If CNTEN = VIL then 'D1' would be written into 'A1' at this point. 3. Data output is available at a tCD after the SR/W = VIH is clocked. The RST sets SR/W = LOW internally and therefore disables the output until the next clock. 4. SCE = VIL throughout all cycles. 5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point. 6. SR/W = VIL.
6.42 19
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port - Reset Timing
tRSPW RST tRSRC R/W, SR/W CMD (4) or (UB + LB) tWERS tRSFV
EOB(1 or 2)
Flag Valid
3099 drw 25
Random Access Port Restart Timing of Sequential Port(1)
0.5 x tCYC tFS SCLK
R/W
(2)
2-5ns 6-7ns
CLR Block
(3)
(Internal Signal)
3099 drw 26
NOTES: 1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5). 2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case 5). 3. CLR is an internal signal only and is shown for reference only. 4. Sequential port must also prohibit SR/W or SCE from being LOW for tWERS and tRSRC periods or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
20
IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Ordering Information
IDT 70824 Device Type X Power XX Speed X Package X Process/ Temperature Range Blank I(1) B G PF 20 25 35 45 S L 70824 Commercial (0C to +70C) Industrial (-40C to +85C) Military (-55C to +125C) Compliant to MIL-PRF-38535 QML 84-pin PGA (G84-3) 80-pin TQFP (PN80-1) Commercial Only Commercial Only Commercial & Military Commercial & Military Standard Power Low Power 64K (4K x 16) Sequential Access Random Access Memory
Speed in nanoseconds
3099 drw 27
NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For specific speeds, packages and powers contact your sales office.
Datasheet Document History
3/8/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 Added additional notes to pin configurations Changed drawing format Replaced IDT logo Page 3 Added "Outputs" in Sequential pin description table Changed 200mV to 0mV in notes CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6166 fax: 408-492-8674 www.idt.com
6.42 21
6/4/99: 11/10/99: 4/18/00:
for Tech Support: 831-754-4613 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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